ECEN 468 Advanced Digital System Design

ECEN 468 Advanced Digital System Design

Spring 2017

Dr. Jiang Hu
Email: jianghu "at"
Phone: 847-8768
Office: 333L WEB
Office hours: 3-4pm Tuesday, 10-11am Friday or by appointment
Tu/Th 8:00-9:15am, THOM 122
Teaching Assistant
Chaofan Li, chaof "at"
Lab webpage
Course Description
This course is mainly to provide students with a system perspective of chip design. System complexity growth is a fundamental technology trend that will continue for a foreseeable future. In this regard, SystemC is a very helpful means for electronic system level (ESL) design and transaction-level modeling. It is getting increasingly popular in chip design industry and likely to become de facto standard in future. The first half of this course and its labs are dedicated to learning and practicing how to use SystemC for hardware modeling. A simple image processing processor design is employed as the platform for the labs. In the second half of this course, this design is synthesized into logic level circuits through Verilog descriptions. Besides the system-level perspective, typical chip component designs, such as memory, bus, UART, are covered. This course also offers a taste of behavioral modeling of analog component (such as PLL) using Verilog-AMS.
No textbook.
ECEN 248 or equivalent, C/C++ language
Homework 10%, Midterm1 20%, Midterm2 20%, Labs 50%

Lecture Agenda (tentative)
  1. Introduction
  2. SystemC quick start
  3. SystemC concurrency
  4. SystemC processes
  5. UART
  6. SystemC channels and signals
  7. SystemC interfaces and ports
  8. Bus architecture
  9. SystemC dynamic processes and design hierarchy
  10. SystemC utilities
  11. Edge detection algorithm
  12. SystemC data types and STL
  13. Transaction-level modeling
  14. OSCI TLM
  15. Design verfication methodology
  16. SystemC verfication extensions
  17. RTL (Register Transfer Level) design
  18. Behavior level design
  19. Logic design with Verilog
  20. Verilog data types
  21. Verilog simulation and testbench
  22. Verilog behavioral descriptions
  23. Verilog finite state machines
  24. Verilog synthesis of combinational logic
  25. Verilog synthesis of sequential logic
  26. Verilog operators
  27. Verilog delay models
  28. Verilog: synthesis of language constructs
  29. Verilog user defined primitives
  30. Verilog switch level models
  31. Basics of Verilog-AMS
  32. Mixed-signal models
  33. Phase-locked loops
  34. Chip I/O design
  35. High-speed links
  36. RTL optimization


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