Instructor/Organizer: Dr. Peng Li Time: 3:55pm – 5:10pm Tuesday (backup:
3:55pm – 5:10pm Thursday) Location: 103 Zachry Policy: To receive the
full credit for this course, you must meet the following requirements: 1.
Miss no more than three
seminars. 2.
Complete a brief report for each seminar in class. Report forms
will be distributed at the beginning of each seminar. The report is due
immediately after the seminar and must be signed by the student. The report form can be downloaded from: dropzone.tamu.edu/~pli/ECEN681Fall09/681-644-report.pdf.
The report should be brief while
highlighting the key points from each seminar. Tentative schedule: September 1, 2009 First week of
the semester, no seminar. September 8, 2009 Dr. Gwan Choi, (ECE Dept.) Low-Power
Embedded Codec Architecture for Mobile Multimedia Devices ABSTRACT Future personal
mobile devices that will evolve out of the current iPhones
and their alternatives will require low-power hardware compositions that
deliver a set of increasingly sophisticated combination of communication and
application functions. In no time these devices will be made up out of single
chip solutions to cut cost and extend battery life. Our research is aims to
put together a unified architecture that meets performance and power
requirements of these components by carefully stitching together the data,
algorithm, architecture, and implementation solutions. I will present one or
two examples of design approaches recently proposed. Joint work
with: Yoonseok
Yang, Weihuang Wang (Broadcom), Sanghoan
Chang (Samsung) Bio: Gwan Choi is Associate
Professor of Electrical Engineering and has received all his degrees in
Electrical and Computer Engineering from University of Illinois
Urbana-Champaign. He has worked at Cray Research, Tandom
Computers, and was a visiting Scientist at NASA Langley Research Center in
1991. He has won a number of research grants from NSF, NASA, IBM, AT&T,
LSI Logics, Texas State, and several startup
companies. He has won NSF CAREER award in 1997. His research interests include
communication circuits, multimedia systems, low-power VLSI design, design for
reliability, sensor network design, self-healing circuits, and ASIC. September 15, 2009 Dr. Alex Sprintson,
ECE/TAMU Wireless Network
Coding for Cooperative Data Exchange ABSTRACT We consider the
problem of data exchange by a group of closely-located wireless clients. In
this problem each client holds a set of packets and needs to obtain all the
packets held by the other clients. Each of the clients can broadcast the
packets in its possession (or a
combination thereof) via a noiseless broadcast channel. The goal is to
minimize the total number of transmissions, assuming that the clients can
cooperate with each other and are fully aware of the packet sets available to
other clients. This problem arises in many practical settings, such as
peer-to- peer systems and wireless data broadcast. We show upper and lower bounds on the
optimal number of transmissions and present an efficient algorithm with
provable performance guarantees. We show possible extensions of this problem
to single-hop and multi-hop wireless settings. Bio: Dr.
Sprintson is an Assistant Professor in the department of Electrical and
Computer Engineering at Texas A&M University. He received his B.Sc.
degree (summa cum laude), M.Sc. and Ph.D. degrees in Electrical Engineering
from the Technion - Israel Institute of Technology,
Haifa, Israel, in 1995, 2001 and 2003, respectively. From 2003 to 2005 he was
a postdoctoral research fellow at the California Institute of Technology. Dr.
Sprintson's research interests lie in the general
area of communication networks with a focus on network survivability, QoS routing, and network coding. Current honors include
having received the Wolf Award for Distinguished Ph.D. students and the Viterbi Postdoctoral Fellowship. He is an Associate
Editor for IEEE Communications Letters and has been a member of the Technical
Program Committee for IEEE Infocom 2006-2010. September 22, 2009 No seminar Dr. Sani Nassif, IBM Austin Research Lab (Host: Dr. Peng Li) Future
Technology Challenges: Variability and Resilience ABSTRACT Silicon
technology is becoming more complex and expensive to develop. This explains the
slowdown and consolidation in our industry, but also presents some important
challenges. This talk will focus on two of those: increasing variability and
decreasing resilience. The first is an old topic, but one where some new
results are making some standard assumptions no longer true. The second is a
new area where a number of interesting research opportunities exists. Bio: Sani received his Bachelors degree with Honors from the
American University of Beirut in 1980, and his Masters and PhD degrees from
Carnegie-Mellon University in 1981 and 1985 respectively. He then worked for
ten years at Bell Laboratories in the general area of technology CAD,
focusing on various aspects of design and technology coupling including
device modeling, parameter extraction, worst case analysis, design
optimization and circuit simulation. While at Bell Labs, working under Larry
Nagel -the original author of Spice, he led a large team in the development
of an in-house circuit simulator, named Celerity, which became the main
circuit simulation tool at Bell Labs. In January
1996, he joined the then newly formed IBM Austin Research Laboratory (ARL),
which was founded with a specific focus on research for the support of
computer systems. Sani currently manages the tools and technology department
at ARL, which is focused on design/technology coupling and includes
activities in: model to hardware matching, simulation and modeling, physical
design, statistical modeling, statistical technology characterization and
similar areas. Sani has
authored numerous conference and journal publications, and delivered many
tutorials at top conferences. He has received four Best Paper awards,
authored invited papers to ISSCC, IEDM, ISLPED, HOTCHIPS, and CICC, given
invited talks at Texas A&M University, RICE University, UCSB, UC Berkeley
and Kyoto University. He has given Keynote and Plenary presentations at Sasimi, ESSCIRC/DERC, BMAS, SISPAD, SEMICON, PATMOS and
ICCV. He is an IEEE Fellow, a member of the ACM and AAAS, and has a total of
44 patents. Sani is a member of the IBM Academy of Technology. Dr. Nassif was
the General chair of the ICCAD conference in 2008. He has previously also
served on the technical program committee of DAC and ISQED, and on the
executive committee of ISPD. He has received the Penrose award (given to one
outstanding graduate from the American University of Beirut), the
Distinguished Member of Technical Staff award from Bell Labs, two Research
Accomplishment Awards from IBM, and the SRC Mahboob-Khan
Outstanding Mentor awards from the SRC. Sani represents
IBM as a member of the SRC Science Area Coordinating Committee for CAD and
Test, and chaired the committee in 2006. He maintains strong ties with
academia, and has participated in numerous PhD committees for students from MIT,
CMU, Univ. Minnesota, Univ. Texas Austin, UCSB, UCI, and Univ. Michigan. September 29, 2009 Dr. Juergen Hahn (Dept. of Chemical Engineering) DEVELOPING
IMPROVED MODELS OF SIGNAL TRANSDUCTION PATHWAYS VIA SYSTEMS BIOLOGY ABSTRACT Gaining an
improved understanding of the molecular mechanisms involved in the acute
phase response (APR) in the liver upon trauma or injury can lead to improved
treatment of complications arising from inflammatory disorders. The dynamics
of expression and interaction of the IL-6 signaling pathway molecules is a
key factor of the phenotypical characteristic of
the APR, as IL-6 has been identified as one of the systemic inflammatory
mediators involved in the regulation of the hepatic APR. This work
develops and analyzes a comprehensive mathematic model for signal
transduction through the JAK/STAT and the MAPK signaling pathways in hepatocytes stimulated by IL-6. Interactions among the
two signaling pathways are systematically investigated using sensitivity
analysis in order to ultimately derive and validate an improved model. An
important aspect of this work is the novel use of sensitivity analysis for
determining which parts of the model may benefit from further model
refinement, whereas traditionally sensitivity analysis has been applied to
determine the contribution of parameters of an existing model to the dynamic
behavior, i.e., such that the important parameters should be estimated from
experimental data. While the exact nature of the additional mechanisms to
include depends upon biological insight into the model, sensitivity analysis
indicates which parameters may be masking more detailed mechanisms of
importance to the model’s predictions. In this work,
results from the sensitivity analysis are used to determine a location for
including a (previously) hidden feedback loop between twice phosphorylated ERK and SOS as parameters contributing to
reactions affecting these proteins were computed to be important.
Additionally, experiments with GFP reporter cells were carried out where the
amount of observed fluorescence is quantified to determine a profile for the
concentration of GFPs. An inverse problem is formulated and solved that
determines the transcription factor concentration from the measured
fluorescence intensity profiles. These experimental results are compared to
simulation data with the original and the newly developed model and were
found to be in excellent agreement with the model derived in this work. BIO: Juergen Hahn received
his diploma degree in engineering from RWTH Aachen, Germany, in 1997, and his
MS and Ph.D. degrees in chemical engineering from the University of Texas,
Austin, in 1998 and 2002, respectively. Afterwards, he was a post-doctoral
researcher at the chair for process systems engineering at RWTH Aachen,
Germany. He joined the department of chemical engineering at Texas A&M
University, College Station, in 2003 and has been promoted to Associate
Professor in 2009. His research interests include systems biology and process
modeling and analysis with over 50 articles and book chapters in print. Dr.
Hahn is a recipient of a Fulbright scholarship (1995/96), received the Best
Referee Award for 2004 from the Journal of Process Control, and the CPC 7
Outstanding Contributed Paper Award in 2006. He is currently serving as an
associate editor for the journal Control Engineering Practice. October 6, 2009 Dr. Frank Liu, IBM Austin Research Lab (Host: Dr. Peng Li) Information Management in DFM Abstract Process
variation is a critical challenge to the scaling of CMOS technology.
Traditionally Design-for-Manufacturability (DFM) is considered as the
practice to amend designs so that an acceptable manufacturing yield can be
achieved. As the scaling continuous, DFM is emerging as a key enabler for
sustainable scaling. In this talk, I will discuss the implication of DFM on
design productivity, another important aspect of continuous scaling. I will
make the argument that adequate abstraction is a key step to balance the two
aspects of VLSI design. Bio: Frank Liu received his
Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon
University in 1999. Currently he is a Research Staff Member at IBM Austin
Research Lab. His research interests include variability modeling,
computational lithography, circuit analysis. He has
authored or co-authored over 40 conference and
journal papers and holds dozens of U.S. and international patents. He has
served on the Technical Program Committees of ICCAD, ASP-DAC, CICC and ISCAS,
and as the General Chair of the IEEE/ACM TAU workshop. He is a senior member
of IEEE. October 13, 2009 Dr. Peng Li, ECE/TAMU Parallel VLSI CAD: Exploring Parallelisms on Multi-core and
Graphics Processors Abstract: The emergence of
multi-core processors and hardware accelerators (e.g. GPUs) is rapidly
changing the landscape of computing. The affordability of such hardware
platforms offers new computing opportunities while imposing challenges in the
design and implementation of efficient parallel algorithms. In this talk, I
will highlight our recent work on exploiting these new parallel computing
platforms for a number of computationally intensive VLSI CAD applications. I
will show how to facilitate parallel circuit simulation with parallelizable
numerical preconditioning techniques and other forms of intra and
inter-algorithm parallelisms. Fast large power grid analysis on GPU-based
SIMD processors, involving interplays between algorithm design, SIMD
architecture consideration and code tuning, will be presented. Finally, a
search-based parallel clock-mesh optimization approach will be highlighted. Bio: Li received the Ph.D. degree in electrical and computer
engineering from Carnegie Mellon University in 2003. His research interests
are in the general areas of VLSI systems, design automation and parallel
computing. His work has been
recognized by various distinctions including two IEEE/ACM Design Automation
Conference (DAC) Best Paper Awards in 2003 and 2008, four best paper award nominations
from IEEE/ACM Int. Conf. on CAD (ICCAD), two SRC Inventor Recognition Awards
in 2001 and 2004, the MARCO Inventor Recognition Award in 2006, the National
Science Foundation CAREER Award in 2008, and the ECE Outstanding Professor
Award from Texas A&M University in 2008.
He is an Associate Editor for IEEE Transactions on CAD and IEEE
Transactions on Circuits and Systems II. He has been on the committees of
many international conferences and workshops including DAC, ICCAD, ISQED, ISCAS, TAU and VLSI-DAT as well as the selection
committee for ACM Outstanding Ph.D. Dissertation Award in Electronic Design
Automation. He has served as the technical program committee chair for the
ACM TAU Workshop in 2009 and general chair for the 2010 Workshop. Additional CE seminar: Room 103 Zachry, Friday, October 16,
2009, 2:30 p.m. Mr. Jerry Hayes/IBM, Host: Dr. Peng Li Future Technology Challenges, Variability and Resilience Abstract: The
design/manufacturing interface is becoming ever more complex, driving the need
for innovation in modeling to adequately capture the technology during chip
level design. In this presentation we
look at issues driving technology complexity and future trends to address
this complexity. BIO: Jerry Hayes obtained a
MSEE from the University of Arizona and has been with IBM for 15 years. His activities at IBM include developing
chip level timing methodologies for addressing process variability that
resulted in the variation aware timing and statistical timing flow used by
IBM ASICs. Recently, his focus has been on developing
test structures for characterizing and modeling process variability that can
be used to bring higher visibility of the manufacturing process to chip level
design for yield optimization. October 20, 2009 Yifang Liu,
(Ph.D. candidate, ECE Dept.) Fast Gate Sizing and Vt Assignment
Method for Power Efficient High Performance Circuits ABSTRACT Gate sizing and
threshold voltage (Vt) assignment are popular
techniques for VLSI circuit timing and power optimization. Existing methods,
by and large, are either sensitivity-driven heuristics or based on discretizing continuous optimization solutions.
Sensitivity-driven heuristics are easily trapped in local optimum and the discretization may be subject to remarkable errors. In
this talk, we propose a systematic combinatorial approach for simultaneous
gate sizing and Vt assignment. The core idea of
this approach is Joint Relaxation and Restriction (JRR), which employs
consistency relaxation and coupled bi-directional solution search. The
process of joint relaxation and restriction is conducted iteratively to
systematically improve solutions. Our algorithm is compared with a
state-of-the-art previous work on benchmark circuits. The results from our
algorithm can lead to about 22% less power dissipation subject to the same
timing constraints. With the
complexity of VLSI circuit keeps increasing, efficient circuit optimization
is crucial to meet the time-to-market requirement. We utilize massive GPU
parallel computing power to speedup the JRR method.
Both the algorithmic and implementation aspect of this parallel computing
scheme are explained. Experiments achieves up to 49x speedup. Bio: Yifang Liu is currently
a Ph.D. candidate in the department of Electrical and Computer Engineering at
Texas A&M University. His research interests include design and analysis
of algorithms, high performance computing, combinatorial, numerical and
statistical optimization, and computer-aided design for VLSI circuits. October 27, 2009 Dr. Yiyu Shi (Host: Dr. Jiang Hu) Statistical Load Current Profiling for Power Integrity Driven
Design Methodologies Abstract: Load Current
Profiling has been a critical issue for power integrity analysis and
verification. For efficiency concerns, the lengthy current profile obtained
from extensive simulation should not be used directly. On the other hand,
assuming maximum load current at all time is too pessimistic and can lead to
significant over-design, given the temporal correlation between clock cycles,
the logic-induced correlation between different ports, and the current
variation due to L_{eff} variation with spatial
correlation. This talk will introduce a statistical load current model which
can efficiently yet accurately capture those correlations. It can also be
used to predict future load current profile with good accuracy. We will show
that the model can find its applications in many design problems, including
the decoupling capacitance (decap) budgeting and
runtime resonance noise suppression. We will also show its potential
application in battery powered systems, which are of increasing interest with
the development of renewable energy. Bio: Yiyu Shi
received his B.S. degree (with honor) in electronic engineering from Tsinghua University, Beijing, China in 2005, the M.S
(with honor) and Ph.D. degree in electrical engineering from the University
of California, Los Angeles in 2007 and 2009 respectively. His main research interests include
numerical and statistical modeling for analog and mixed-signal circuits,
large-scale optimization and combinatorial mathematics. He holds one U.S.
patent and has authored or co-authored over 30 conference and journal papers,
including Best Paper Finalists in IEEE/ACM Design Automation Conference
(2006, 2009), IEEE/ACM International Conference on Computer-aided Design
(2007), IEEE International Conference on Computer Design (2008) and IEEE/ACM
Asia and South Pacific Design Automation Conference (2009) . He is the
recipient of the outstanding M.S. Student from Electrical Engineering Dept.,
UCLA in 2007 and the IBM Invention Achievement Award in 2009. For more information, please visit
http://www.ee.ucla.edu/~yshi. November 3, 2009 Dr. Sam Palermo
(ECE Dept.) An Overview of High-Speed I/O Design ABSTRACT This talk provides
an overview of system and circuit design issues relevant to high-speed I/O
transceivers used for chip-to-chip communication. First, the dominant sources of electrical
interconnect channel loss, crosstalk, and noise are covered. Next, circuit implementations of serial I/O
drivers/receivers, equalization techniques, and timing generation/recovery
are detailed. The talk concludes with
a brief discussion of current/future I/O research directions and an introduction
to optical I/O. Bio: Samuel Palermo received
the B.S. and M.S. degree in electrical engineering from Texas A&M
University, College Station, TX in 1997 and 1999, respectively, and the Ph.D.
degree in electrical engineering from Stanford University, Stanford, CA in
2007. From 1999 to
2000, he was with Texas Instruments, Dallas, TX, where he worked on the
design of mixed-signal integrated circuits for high-speed serial data
communication. From 2006 to 2008, he was with Intel Corporation, Hillsboro,
OR, where he worked on high-speed optical and electrical I/O architectures.
In 2009, he joined the Electrical and Computer Engineering Department of
Texas A&M University where he is currently an assistant professor. His
research interests include high-speed electrical and optical links, clock
recovery systems, and techniques for device variability compensation. Dr.
Palermo is a member of IEEE and Eta Kappa Nu. November 10, 2009 Dr. Andrew
Jiang (CSE Dept.) Data Movement and Rewriting in Flash Memories Abstract: In this talk, I
will discuss two new topics on coding for data storage in flash memories. The
applications of flash memories have expanded widely in recent years, and
flash memories have become the dominating member in the family of
non-volatile memories. Like magnetic recording and optical recording, flash
memories have their own distinct properties,
including recursive programming, block erasure, etc. These distinct
properties introduce very interesting coding problems that address many
aspects of a successful storage system, which include efficient data
modification, error correction, high density storage, and more. In this talk,
I will introduce two newly studied topics, including how to use coding to
efficiently move data in NAND flash memories, and how to rewrite data efficiently
using a rewriting code called the trajectory code. In both cases, the
objective is to minimize the number of block erasures, in order to improve
the performance and longevity of flash memories. Bio: Anxiao (Andrew) Jiang has been an assistant professor in the
Computer Science and Engineering Department of Texas A&M University since
2005. He received his Ph.D. and M.S. in Electrical Engineering at Caltech and
his B.E. in Electronic Engineering at Tsinghua
University. He received the National Science Foundation CAREER Award for his
pioneering work on coding for flash memories. His research interests include
information theory, data storage and algorithm design. November 17, 2009 Dr. Paul Gratz (ECE Dept.) Asynchronous Bypass Channels: Improving Power and Performance in
GALS and DVFS supporting NoCs ABSTRACT In this talk I
will present Asynchronous Bypass Channels (ABCs), a novel
router microarchitecture for Networks-on-Chip (NoCs). ABCs offer
superior performance versus the typical, synchronizing router designs seen in
NoCs which support either dynamic
voltage and frequency scaling (DVFS) or globally synchronous, locally
asynchronous (GALS) clocking schemes for reduced power consumption. Power consumption has become a first order
constraint in modern VLSI design. DVFS reduces
power consumption by dynamically changing the frequency and voltage of nodes
within the network to match the needs of the application, while GALS clocking
schemes reduce power consumption by removing the need for balanced clock
trees. Both approaches, however, imply
that packets must be synchronized at every hop, yielding high latencies and
poor performance. Our approach
features ABCs at intermediate nodes to avoid per-hop synchronization delay
and approach the electrical latencies of the wires. We also propose a new network topology that
leverages the advantages of the bypass channel offered by our router
design. Our experiments show that our
design improves performance by up to 26% at low loads and increases
saturation throughput by up to 11% of a conventional synchronizing design with
similar resources and power consumption. Bio: Paul V. Gratz is an assistant professor in the Department of
Electrical and Computer Engineering at Texas A&M University. His research interests include high
performance computer architecture, processor memory systems, on-chip
interconnection networks, and distributed systems. At this year's International Conference on
Architectural Support for Programming Languages and Operating Systems (ASPLOS
'09), Dr. Gratz co-authored "An Evaluation of the TRIPS Computer
System," receiving a best paper award.
As a graduate student at the University of Texas at Austin, he
designed and implemented the L2 cache sub-system of the TRIPS processor, and
the network-on-chip that interconnects the cache banks and processors of a
TRIPS chip. Dr. Gratz
received a BS and MS in electrical engineering from the University of Florida
and spent five years as a design engineer at Intel corporation. November 19, 2009 (additional CE seminar) Dr. Jaeha Kim, EE Dept., Stanford
University (Host: Dr. Peng Li) 342 Zachry, 11:00am Title: Leveraging Designer’s Intent: A Path Toward Simpler
Analog CAD Tools Abstract: Leveraging the
Boolean intent of digital circuits has enabled a wide set of CAD tools that
helped increase the productivity of digital designers. To increase analog
designers’ productivity requires a similar encapsulation of designer’s intent
for analog circuits. We argue that linear system models serve this role for
almost all analog circuits, while the variables of these models may be in
some transformed domains, rather than being the direct voltage/current
waveforms of the circuits. We show how using these models enable new ways to
design, optimize, and validate mixed-signal circuits. Even systems that reach
steady states only in a stochastic sense can be analyzed as linear systems.
Then a remaining issue is to ensure that the non-linear circuit reaches the
intended “linear” operating point during start-up, which can be addressed by
global convergence analysis. Bio: Jaeha Kim is currently an Acting
Assistant Professor at Stanford University and his research interests include
low-power mixed-signal systems and their design methodologies. He received
the B.S. degree in electrical engineering from Seoul National University,
Korea in 1997 and received the M.S. and Ph.D. degrees in electrical
engineering from Stanford in 1999 and 2003, respectively. Previously, he was
with True Circuits as Circuit Designer, with Seoul National University as
Post-doctoral Researcher, and most recently with Rambus,
Inc. as Principal Engineer. Dr. Kim is a recipient of the Takuo
Sugano award for outstanding far-east paper at 2005 International Solid-State
Circuits Conference (ISSCC). November 24, 2009 Dr. Byung-Jun
Yoon (ECE Dept.) December 1, 2009 TBD December 8, 2009 Redefined day,
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