Layout and Parasitic Information for ISCAS Circuits

We developed a standard-cell library and performed layout, parasitic extraction and delay evaluation for ISCAS85 benchmark circuits. For questions and suggestions, please contact Xiang Lu or Prof. Weiping Shi.

Technology

TSMC-180nm, layer map

Standard Cell Library

Library Exchange Format (LEF) File
Logical Description: verilog
Transistor Description: standard cells, CMOS model
Cell List:

Combinational cells:

Inverters: inv_1
Buffers: buf_1
AND/NAND: and2_1, and3_1, and4_1, and5_1, and8_1, and9_1, nand2_1, nand3_1, nand4_1, nand5_1, nand8_1, nand9_1
OR/NOR: or2_1, or3_1, or4_1, or5_1, or8_1, or9_1, nor2_1, nor3_1, nor4_1, nor5_1, nor8_1, nor9_1
XOR: xor2

Sequential cells:

D flip-flop: dff

Benchmark Circuits

ISCAS85

Circuit	Netlist	Layout	Parasitic	Delay	Coupling Capacitance
c432	verilog, bench	def, gds2	dspf	sdf	text
c499	verilog, bench	def, gds2	dspf	sdf	text
c880	verilog, bench	def, gds2	dspf	sdf	text
c1355	verilog, bench	def, gds2	dspf	sdf	text
c1908	verilog, bench	def, gds2	dspf	sdf	text
c2670	verilog, bench	def, gds2	dspf	sdf	text
c3540	verilog, bench	def, gds2	dspf	sdf	text
c5315	verilog, bench	def, gds2	dspf	sdf	text
c6288	verilog, bench	def, gds2	dspf	sdf	text
c7552	verilog, bench	def, gds2	dspf	sdf	text

* Nets that might involves in bridge faults can be identified from the coupling capacitance information.

ISCAS89: coming now...... (only s15850 is completed for test)

Circuit	Netlist	Layout	Parasitic	Delay	Coupling Capacitance
s1488	verilog, bench	def, gds2	dspf	sdf	text
s38417	verilog, bench	def, gds2	dspf	sdf	text
s35932	verilog, bench	def, gds2	dspf	sdf	text
s38584	verilog, bench	def, gds2	dspf	sdf	text
s15850	verilog, bench	def, gds2	dspf	sdf	text

Last Updated: Nov. 11, 2004